Dr Jafar (Seyed Ruhollah) Shojaii

Biography

I am the head of the Nanoscale Electronics Group with a board research expertise and interest in developing electronics systems for science applications, particularly for defence, space and particle physics experiments.

From 2012 until 2023, I was a member of the ATLAS experiment at CERN, where I had significant contributions to the upgrade of the Large Hadron Collider detectors, including the design and test of VLSI processor chips in CMOS technology for the ATLAS trigger system, rad-hard read-out CMOS electronics for particle sensors and design/test of new generations of particle pixel detectors in nanoscale CMOS technology.

I am the Lead Chief Investigator of a Defence Science and Technology Group (DSTG) program to develop a new generation of rad-hard semiconductor chips against Direct Energy Weapons for defence and to resist space radiations for satellites. My work on rad-hard semiconductor electronics includes the design of ASIC chips at the transistor level and characterization/radiation testing of the chip prototypes under heavy ions and high-energy proton beams by using accelerator machines in collaboration with CERN, ANSTO and the University of Kyoto. 

I graduated from the University of Milan. I was with the Italian National Institute of Nuclear Physics (INFN) and CERN from 2012 to 2017 and with the University of Melbourne from 2017 to 2022. Also, I am an honorary fellow at the Italian National Institute of Nuclear Physics and the University of Melbourne.