Overview

After successfully completing this unit, students should be able to apply a variety of application-oriented digital electronics design skills, including:
• The design of significant combinatorial & synchronous digital systems
• The use of Electronic Design Automation (EDA) tools for design, analysis and simulation

Requisites

Teaching periods
Location
Start and end dates
Last self-enrolment date
Census date
Last withdraw without fail date
Results released date

Learning outcomes

Students who successfully complete this unit will be able to:

  • Design and implement combinatorial digital circuits using gates and logic components such as multiplexers and decoders (K2, K3, S1, S2, S3)
  • Design and implement synchronous digital systems including counters, arbitrary sequence counters and general state machines (K2, K3, S1, S2, S3)
  • Design and implement standard Mealy and Moore style state machines (K2, K3, S1, S2, S3)
  • Design and implement in programmable logic moderately complex digital systems that incorporate control (ULO 3) and data operations (K2, K3, S1, S2, S3)
  • Use a hardware description language (VHDL) to implement ULOs 1, 2, 3 and 4 (K2, K3, S1, S2, S3)
  • Apply Electronic Design Automation (EDA) tools to carry out ULOs 1,2,3,4 and 5 (S1, S2, S3)
  • Appreciate real-world considerations in the design of digital circuits e.g. non-ideal inputs, timing requirements and hazards (K2, K3, S1, S3)
  • Analyse a problem scenario leading to a design and implementation based upon digital logic using appropriate techniques (S1, S2, S3)

Teaching methods

Hawthorn

Type Hours per week Number of weeks Total (number of hours)
On-campus
Lecture		3.00 12 weeks 36
On-campus
Class		1.00 11 weeks 11
On-campus
Lab		1.00 14 weeks 14
Online
Directed Online Learning and Independent Learning		1.00 11 weeks 11
Unspecified Activities
Independent Learning		6.50 12 weeks 78
TOTAL150

Assessment

Type Task Weighting ULO's
ExaminationIndividual 60% 1,2,3,4,5,8 
ProjectGroup 30% 1,2,3,4,5,6,7,8 
Tutorial ExercisesIndividual 10% 1,2,3,4,5,8 

Hurdle

As the minimum requirements of assessment to pass a unit and meet all ULOs to a minimum standard, an undergraduate student must have achieved:

(i) an aggregate mark of 50% or more, and(ii) at least 40% in the final exam.Students who do not successfully achieve hurdle requirement (ii) will receive a maximum of 45% as the total mark for the unit.

Content

  • Boolean Algebra and Logic Design
  • Simplification of Boolean Functions
  • Logic Components
  • Programmable Logic Devices
  • Synchronous Sequential Logic
  • Hardware Description Languages (VHDL)
  • Electronic Design Automation tools

Study resources

Reading materials

A list of reading materials and/or required textbooks will be available in the Unit Outline on Canvas.